The present invention relates generally to integrated circuits and, more particularly, to reset circuitry for integrated circuits.
With the increased complexity of digital design, the reset architecture has also become very complex. In a typical SOC, a “global chip reset,” which resets most of the system, is a combination of multiple reset sources which can be generated either by software or hardware. Power On Reset (POR), Low Voltage Detect reset, Watchdog Timeout reset, Debug reset, Software reset, and Loss of Clock reset are some examples which cause the assertion of a global reset. However, there can be some parts of the system which are not in the reset state even with assertion of the global reset. Some examples are: time keeping functionality, calendaring features, and reset status registers, which capture the reset event causing the global reset. So there is the possibility that a part of the system which asynchronously goes into reset state can corrupt another other part not in a reset state.
Reset procedures may be synchronous (with a system clock) or asynchronous. Synchronous resets are based on the premise that the reset signal will affect or reset the state of a flip-flop only on the active edge of its clock input. It is not uncommon to gate the system clock in order to save power and such cases, asynchronous reset is preferred in order to avoid the situation of the clock being disabled at the same time as an assertion of a reset. However, asynchronous reset is not without its drawbacks. Consider first and second flip-flops where the output (“Q”) of the first flip-flop provides the input (“D”) to the second flip-flop and each flip-flop has a different reset source. The assertion of a reset to the first flip-flop while no reset is being asserted to the second flip-flop can cause meta-stability in the second flip-flop if the input to the second flip-flop changes within its set-up or hold window. Further, if the output of the second flip-flop is used in some other part of the system, then this meta-stability can cause functional failures such as memory data corruption or software programmable configuration register corruption in some circumstances. In a sequential design, if the reset of a source register is different from the reset of destination register (as in the example of the two flip-flops mentioned above), even though the data path may be in same clock domain, an asynchronous crossing path will exist and may cause meta-stability at a destination register. This effect is termed herein as a “Reset Domain Crossing” (RDC).
Hence it would be advantageous to provide a means for resolving these reset domain crossing issues.
Apart from the issues related to asynchronous reset assertion mentioned above as reset domain crossings, there are issues related to asynchronous reset de-assertion as well. If the asynchronous reset is de-asserted within the setup or hold window of the clock of flip-flop then there could be meta-stability at the flip-flop's output. Another issue is reset propagation delay to different device locations, especially from the core of an SOC to the periphery of the integrated circuit. Consider two sequential elements with different propagation delays from the reset signal source. After the assertion of the reset signal, these sequential elements both get reset. Then the reset signal de-asserts just before a clock edge. The sequential element with a short propagation delay comes out of the reset state following the clock edge. The other element with a long propagation delay, however, may miss the clock edge, so it remains in reset state, damaging the circuit performance. This problem is more pronounced when sequential elements are distributed in remote areas of the circuit, such as in the peripheral areas for I/O (Input/Output) modules.
Hence it would also be advantageous to provide a means for resolving the problems related to asynchronous reset de-assertion.